Product Summary

The XC2S50-5PQ208C is a Field-Programmable Gate Array. It gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S50-5PQ208C offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200 MHz. Features of the XC2S50-5PQ208C include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.

Parametrics

XC2S50-5PQ208C absolute maximum ratings: (1)VCCINT, Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO, Supply voltage relative to GND:–0.5 to 4.0 V; (3)VREF, Input reference voltage: –0.5 to 3.6 V; (4)VIN, Input voltage relative to GND: –0.5 to 5.5 V at 5V tolerant I/O; –0.5 to VCCO+0.5 V at No 5V tolerance; (5)VTS, Voltage applied to 3-state output 5V tolerant I/O: –0.5 to 5.5 V; No 5V tolerance: –0.5 to VCCO +0.5 V; (6)TSTG, Storage temperature (ambient): –65 to +150℃; (7)TJ, Junction temperature: +125℃.

Features

XC2S50-5PQ208C features: (1)Densities as high as 5,292 logic cells with up to 200,000 system gates; (2)Streamlined features based on Virtex FPGA architecture; (3)Unlimited reprogrammability; (4)Very low cost; (5)Cost-effective 0.18 micron process; (6)Pb-free package options; (7)Low-cost packages available in all densities; (8)Family footprint compatibility in common packages; (9)16 high-performance interface standards; (10)Hot swap Compact PCI friendly; (11)Zero hold time simplifies system timing.

Diagrams

XC2S50-5PQ208C block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
XC2S50-5PQ208C
XC2S50-5PQ208C


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(USD)
Quantity
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