Product Summary

The XC2S400E-6FTG256C is a Field-Programmable Gate Array. It gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S400E-6FTG256C offers densities ranging from 50,000 to 600,000 system gates. System performance is supported beyond 200 MHz. The XC2S400E-6FTG256C is a superior alternative to mask-programmed ASIC. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).

Parametrics

XC2S400E-6FTG256C absolute maximum ratings: (1)Supply voltage relative to GND, VCCINT: -0.5 to 2.0V; (2)Supply voltage relative to GND, VCCO: -0.5 to 4.0V; (3)Input reference voltage, VREF: -0.5 to 4.0V; (4)Input voltage relative to GND (2,3), VIN: -0.5 to 4.0V; (5)Voltage applied to 3-state output, VTS: -0.5 to 4.0V; (6)Storage temperature (ambient), TSTG: -65 to +150℃; (7)Junction temperature, TJ: +125℃.

Features

XC2S400E-6FTG256C features: (1)Second generation ASIC replacement technology; (2)System level features; (3)SelectRAM hierarchical memory; (4)Versatile I/O and packaging; (5)Pb-free package options; (6)Low-cost packages available in all densities; (7)Family footprint compatibility in common packages; (8)19 high-performance interface standards; (9)Up to 205 differential I/O pairs that can be input, output, or bidirectional; (10)Hot swap I/O (CompactPCI friendly); (11)Core logic powered at 1.8V and I/Os powered at 1.5V, 2.5V, or 3.3V; (12)Fully supported by powerful Xilinx ISE development system.

Diagrams

XC2S400E-6FTG256C block diagram

XC2S100
XC2S100

Other


Data Sheet

Negotiable 
XC2S100-5FG256C
XC2S100-5FG256C


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Data Sheet

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Data Sheet

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Data Sheet

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Data Sheet

Negotiable 
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XC2S100-5FGG256C


IC SPARTAN-II FPGA 100K 256-FBGA

Data Sheet

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